1. Field
The present disclosure relates generally to digital systems, and more specifically, to methods and apparatuses for transmitting memory pre-fetch commands over a bus in a processing system.
2. Background
Integrated circuits have revolutionized the electronics industry by enabling new applications which were difficult or impossible to realize with discrete devices. Integration allows complex circuits consisting of millions of electronic components to be packaged into a single chip of semiconductor material. As a result, powerful computation devices such as computers, cellular phones, personal digital assistants (PDAs), and the like may be reduced to hand-held devices.
Integrated circuits are widely used today to implement sophisticated circuitry such as general purpose and specific application processors. A typical integrated processor may include a central processing unit (CPU) with system memory. A high bandwidth system bus may be used to support communications between the two. A bus is typically a shared channel or path between components on an integrated circuit. In addition, there may also be an external bus which may be used to access low latency off-chip memory under control of an on-chip memory controller.
The off-chip memory is generally formatted into pages. A page is normally associated with a row of memory. In most applications, the memory controller is capable of only opening a limited number of pages at a time. An “open page” means that the memory is pointing to a row of memory and requires only a column access command from the memory controller to read the data. To access an unopened page of memory, the memory controller must present a row access command to the memory to move the pointer before presenting a column access command to read the data. As a result, there is a latency penalty for closing a page in memory and opening a new one.
Many CPU implementations include a pre-fetch mechanism to compensate for the high latency typically encountered with off-chip memory devices. These CPUs may be configured to evaluate instruction streams and make requests for pages from the off-chip memory devices that may be needed in the future in order to reduce the latency and improve CPU performance. However, these pre-fetch requests can often be incorrect due to branches in the instruction stream, as well as CPU interrupts. Moreover, once a pre-fetch request has been accepted on the bus, the data will be read from the off-chip memory and transferred on the bus back to the CPU even though the data may no longer be required. This often leads to lower bandwidth on the bus, delaying CPU access to subsequent data from the off-chip memory device as the speculative data is transferred across the bus to the CPU.
The use of pre-fetch commands to interface a CPU to an off-chip memory device has provided a workable solution for many years. However, as the operating speed of CPU continues to increase exponentially, it is becoming increasingly desirable to reduce the latency typically associated with off-chip memory devices.